//`timescale 1ns / 1ps
// `define DLY #1
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    09:52:02 03/31/2021
// Design Name:
// Module Name:    DMA8311
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DMA8311(
	input					clk,
	input					rst_n,
	input					ads_n,
	input					blast_n,
	input			[31:2]	la,
	input					lhold,
	input					lwr_n,
	inout			[31:0]	PXI_LD,
	output	reg				lholda,
	output	reg      		ready_n,

	output	reg		[31:0]	data_latch,
	output	reg		[31:0]	addr,
	input			[31:0]	READ_DATA
);

//总线占用请求及响应电路模块（始终响应请求）
always @(posedge clk) begin
	lholda	<= lhold;
end

reg[31:0] local_data;
assign PXI_LD = lwr_n ? 32'bz : local_data;

localparam	IDLE	= 3'h0;
localparam	START	= 3'h1;
localparam	OVER	= 3'h2;

// assign response_finish = (current_state == VALID)? 1'b1 : 1'b0;


reg[2:0] state/*synthesis noprune*/;
always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		state	<= IDLE;
	end else begin
		case (state)
			IDLE: begin
				if (!ads_n) begin
					state	<= START;
				end else begin
					state	<= IDLE;
				end
			end
			START: begin
				if (!blast_n) begin
					state	<= OVER;
				end else begin
					state	<= START;
				end
			end
			OVER: begin
				if (blast_n) begin
					state	<= IDLE;
				end else begin
					state	<= OVER;
				end
			end
			default: ;
		endcase
	end
end


always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		ready_n	<= 1'b1;
	end else begin
		case (state)
			IDLE: begin
				if (!ads_n) begin
					ready_n	<= 1'b0;
				end else begin
					ready_n	<= 1'b1;
				end
			end
			START: begin
				addr	<= la;
				if (!blast_n) begin
					ready_n	<= 1'b1;
				end else begin
					ready_n	<= 1'b0;
				end
			end
			OVER: begin
				ready_n	<= 1'b1;
			end
			default: ;
		endcase
	end
end

reg wr_en,rd_en;
reg[31:0] READ_DATA1;
always @(posedge clk) begin
	case (state)
		START: begin
			if (lwr_n) begin
				data_latch	<= PXI_LD;
				wr_en		<= 1'b1;
			end else begin
				local_data	<= READ_DATA1;
				READ_DATA1	<= READ_DATA1 + 1'b1;
				rd_en		<= 1'b1;
			end
		end
		default: begin
			data_latch	<= data_latch;
			wr_en		<= 1'b0;
			rd_en		<= 1'b0;
			READ_DATA1	<= 32'h0;
			local_data	<= 32'h0;
		end
	endcase
end

// always@(posedge clk)
// begin
// 	current_state <=`DLY  next_state;
// end

// always@(*)
// begin
// 	case(current_state)
// 	IDLE:begin
// 			if(!ads_n)
// 				next_state = WAIT0;
// 			else
// 				next_state = current_state;
// 		end
// 	WAIT0:begin
// 			next_state = ADDR_LATCH;
// 		end
// 	ADDR_LATCH:begin
// 			if(wren == 1 && rden == 0)
// 				next_state = VALID;
// 			else if(wren == 0 && rden == 1)
// 				next_state = WAIT1;
// 			else
// 				next_state = current_state;
// 		end
// 	WAIT1:begin
// 			next_state = WAIT2;
// 		end
// 	WAIT2:begin
// 			if(data_valid)
// 				next_state = VALID;
// 			else
// 				next_state = WAIT2;
// 		end
// 	VALID:begin
// 			next_state = COMMU_END;
// 		end
// 	COMMU_END:begin
// //			if(blast_n)
// 				next_state = IDLE;
// //			else
// //				next_state = current_state;
// 		end
// 	default:begin
// 			next_state = IDLE;
// 		end
// 	endcase
// end

// always@(posedge clk)
// begin
// 	case(next_state)
// 	IDLE:begin
// 			ready_n		<= `DLY 1;
// 			addr_en		<= `DLY 0;
// 			wren		<= `DLY 0;
// 			rden		<= `DLY 0;
// 			pcie_busy	<= `DLY 0;
// 		end
// 	WAIT0:begin
// 			addr_en		<= `DLY 0;
// 			wren		<= `DLY 0;
// 			rden		<= `DLY 0;
// 			ready_n		<= `DLY 1;
// 			pcie_busy	<= `DLY 0;
// 		end
// 	ADDR_LATCH:begin
// 			addr_en		<= `DLY 1;
// //			addr		<= `DLY {la,2'b0};
// 			addr		<= `DLY la;
// 			pcie_busy	<= `DLY 1;
// 			data_latch	<= `DLY PXI_LD;
// 			if(lwr_n)
// 			begin
// 				wren	<= `DLY 1;
// 				rden	<= `DLY 0;
// 				ready_n	<= `DLY 0;
// 			end
// 			else
// 			begin
// 				wren	<= `DLY 0;
// 				rden	<= `DLY 1;
// 				ready_n	<= `DLY 1;
// 			end
// 		end
// 	WAIT1:begin
// 			ready_n		<= `DLY 1;
// 			addr_en		<= `DLY 0;
// 			addr		<= `DLY addr;
// 			data_latch	<= `DLY data_latch;
// 			wren		<= `DLY 0;
// 			rden		<= `DLY 0;
// 			pcie_busy	<= `DLY 1;
// 		end
// 	WAIT2:begin
// 			ready_n		<= `DLY 1;
// 			addr_en		<= `DLY 0;
// 			addr		<= `DLY addr;
// 			data_latch	<= `DLY data_latch;
// 			wren		<= `DLY 0;
// 			rden		<= `DLY 0;
// 			pcie_busy	<= `DLY 1;
// 		end
// 	VALID:begin
// 			ready_n		<= `DLY 0;
// 			addr_en		<= `DLY 0;
// 			addr		<= `DLY addr;
// 			data_latch	<= `DLY data_latch;
// 			wren		<= `DLY 0;
// 			rden		<= `DLY 0;
// 			pcie_busy	<= `DLY 1;
// 		end
// 	COMMU_END:begin
// 			ready_n		<= `DLY 1;
// 			addr_en		<= `DLY 0;
// 			addr		<= `DLY addr;
// 			data_latch	<= `DLY data_latch;
// 			wren		<= `DLY 0;
// 			rden		<= `DLY 0;
// 			pcie_busy	<= `DLY 0;
// 		end

// 	default:;

// 	endcase
// end

endmodule
